The past approaches described in the following could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in the following are not to be considered prior art to the claims in this application merely due to the presence of these approaches in the following background description.
In the last years, the demand of increasing the semiconductor device integration density has resulted in a reduction of the sizes of the elements used in integrated circuits.
A basic integrated circuit element is the transistor; particularly, in high-density integrated circuits, field-effect transistors are used. The use of integrated transistors in a number of relatively high-power applications, such as liquid crystal display drivers and the like, has made it necessary to manufacture small size transistors that are nevertheless able to withstand relatively high voltages (for example, 10V-70V).
Limitations in the manufacturing of small-size field-effect transistors, for example of the MOS type, often arise from the length of the transistor channel, i.e. the region between the source and drain transistor regions.
A well-defined channel length is important for the correct operation of the MOS transistor; in fact, many electrical characteristic parameters, such as the transconductance, depend on the transistor channel length.
Moreover, as the channel length becomes smaller, the correct operation of the transistor as a whole may be impaired, due for example to short-channel effects, such as punch-through phenomena or a permanently short-circuited channel.
In particular, as far as MOS transistors for relatively high-power applications (hereinafter shortly referred to as power MOS transistors) are concerned, further electrical characteristic parameters that makes the manufacturing of small-size transistors troublesome are the voltages that the power transistor should withstand at its PN junctions; in particular, in order for the MOS transistor to withstand the desired high voltages, these voltages must be lower than the breakdown voltages of the transistor PN junctions.
As known, the breakdown voltage of a PN junction depends on a certain number of design and manufacturing-process parameters, such as the dopant concentration of the regions forming the junction and the width of such regions. Particularly, the breakdown voltage is higher the lower the dopant concentration of the regions forming the junction. Moreover, in case one or both of the regions forming the junction are lightly doped, the width of such regions should be enough to permit the desired size of the depletion area in a reverse bias condition, and this limits the possibility of reducing the integrated circuit area.
A typical MOS transistor has a semiconductor substrate region of a first conductivity type (for example, P-type) that is provided on its surface a gate oxide layer, surmounted by a gate electrode (typically, a polycrystalline silicon layer). The drain and source regions are two diffusion regions of a conductivity type opposite to the first type (for example, N-type) formed in the substrate region, and they are adjacent to the gate electrode. Moreover, two heavily doped regions are formed in the drain and source regions, respectively. These heavily doped regions are adapted to form the source and drain ohmic contacts with the subsequent metallization layers.
The channel region of the MOS transistor develops horizontally between the drain and source regions. In order for the MOS transistor to be able to withstand relatively high voltages at its PN junctions, the source and drain regions should be lightly doped regions. Moreover, the heavily doped regions adapted to form the ohmic contacts should be spaced apart a distance from the gate region. In order to decrease the MOS transistor size, the gate electrode length (i.e., the MOS transistor channel length) should be reduced, but if the channel length is reduced too much, short-channel effects may arise.
Folded-gate MOS transistors (also known in the art as vertical-gate, V-MOS, U-MOS or trench gate MOS transistors) are less affected by short channel effects. In these devices, a trench is formed in a substrate region of a first conductivity type (for example, P-type). The walls of the trench are covered with a gate oxide film, and the trench is then filled with a conductive material adapted to form the gate electrode (typically, a polycrystalline silicon layer). Source and drain regions of a conductivity type (for example, N-type) opposite to the first type are formed in the substrate region at the sides of the trench.
The folded-gate MOS transistor has a channel region developing along the vertical and bottom walls of the trench, between the source and drain regions. In such a way, even if the overall size of the folded-gate MOS transistor is reduced (for reducing the integrated circuit area), the channel region can be kept sufficiently long to prevent the short channel effects.
A U-MOS transistor is disclosed in the U.S. Pat. No. 4,455,740, which also discloses a related manufacturing method and which is incorporated by reference.
It has been observed that a folded-gate MOS transistor realized according to the teachings of U.S. Pat. No. 4,455,740 is not able to withstand high voltages across the substrate-drain and substrate-source junctions, due to the fact that the drain and source regions are heavily doped (N+) diffusion layers, obtained through an ion injection of arsenic into a substrate region of an opposite conductivity type (those N+ diffusion layers will be contacted by the source and drain metal contacts, thus their dopant concentration must be very high, so to form ohmic contacts). The high dopant concentration of the drain and source regions reduces the substrate-source and substrate-drain junctions breakdown voltages, and thus the voltages that can be withstood by such junctions, and this makes the transistors not particularly adapted for power applications.
U.S. Pat. No. 6,586,800, which is incorporated by reference, proposes a trench-gate MOS transistor having a trench that extends from a top surface into a channel-accommodating P-type substrate region. A gate oxide layer covers the walls of the trench, which is filled by a gate electrode. A source region consists of an N-type diffusion layer adjacent to both sides of the trench; a drain region consists of an N-type buried layer under the channel-accommodating substrate region into which the trench partly extends. The drain current is collected through a metallization layer formed under the buried layer, thus at the bottom surface of the structure.
As an alternative to the bottom surface drain contact, a top-surface sinker adapted to collect the drain current may be provided, as for example described in the U.S. Pat. No. 5,124,764, which is incorporated by reference.
In the solutions described in U.S. Pat. Nos. 6,586,800 and 5,124,764, the dopant concentration of the drain region is chosen according to the desired breakdown voltage at the drain-substrate junction.
It has been observed that in both cases, the breakdown voltages are relatively high for the substrate-drain junction, but low for the substrate-source junction. Thus, the known folded-gate power MOS transistors are inherently asymmetric, and this may be a disadvantage, because in many applications (e.g., pass transistors) the source and drain regions should be interchangeable. On the other side, the known folded-gate MOS transistors having a symmetric structure are not adapted to relatively high-power applications.